System-on-chip (SOC) ASIC devices with embedded cores, such as a DSP core or an ARM core, typically have the capability for in-circuit emulation. Emulation includes the monitoring and controlling of the state of such cores. Emulation is a development tool used in debugging hardware/software interactions or interfaces, as well as debugging software failures. Such emulation is typically a pre-production debugging tool, but may also be used for post-production testing.
Existing in-circuit emulation techniques allow the capture and/or control of SOC-internal registers to aid in the integration and/or debugging of the SOC device. These captured register values are provided off-chip with a serial scan chain. If a core that is included within the scan chain is powered off during the emulation process, the scan chain is interrupted. This interruption not only causes the loss of data relative to the powered-off core, but also breaks the scan chain and blocks data from all other cores that are still being emulated from exiting the chip, and prevents new data from flowing into the chip. In short, in a multi-core SOC device, if one or more of the cores are powered down during an emulation operation, the emulation capability for the whole device is destroyed.
For some applications, emulation makes use of IEEE standard 1149.1: Standard Test Access Port and Boundary Scan Architecture, commonly known by the acronym JTAG (for the Joint Test Action Group whose recommendations were used as the basis of the 1149.1 standard).
The main advantage of using such boundary scan technology is that the values on pins may be set and read without physical access. The signals between the SOC device's core logic and the “pins” are intercepted by a serial scan datapath known as the boundary scan register (BSR). In normal operation these boundary scan cells are invisible. However, in test mode the cells can be used to set and/or read values: in external mode these will be the values of the “pins”; in internal mode these will be the values of the core logic.
The serial datapath is communicated into the device through a JTAG serial input pin, through a test access port (TAP) controller (which is effectively a JTAG controller) associated with a first core, out of that TAP controller and into a TAP controller associated with a second core, and so on through a series of TAP controllers, each associated with a different core, and finally out of the device through an output pin. If a particular TAP controller is powered down during an emulation operation, the serial chain of the datapath (which is effectively a long shift register) is blocked at that powered-down TAP controller and the emulation process is corrupted.